This invention relates to a method and apparatus for decimal division.
Among operation instructions, a decimal division instruction is one that requires particularly large operation cycles and for this reason, it is difficult to improve the operation speed.
A heretofore known decimal division system employs two registers A and C, an adder/subtracter 1, a shifter 2, a subtraction count portion 3 and a carry detector 4, as shown in FIG. 1. In order to effect division, a dividend is stored in register A and the divisor, in register C, respectively. The adder/subtracter reduces the dividend by the amount of the divisor 1, and the result 1A is returned to register A through a selector 5. When the result of subtraction proves to be positive or zero, a carry signal is detected by the carry detector 4, and a gate 10 is opened so that the value of the subtraction count portion 3 becomes "1". The content of register C is repeatedly subtracted from the content of register A until the result of subtraction proves to be negative; the result 1A is returned to register A, and the value of the subtraction count portion 3 is incremented by +1 whenever a carry occurs.
When the result of subtraction proves to be negative, the value of the subtraction count portion 3 becomes the result digit, an is set to be the uppermost digit of the quotient. At the same time, the content of register A and that of register C are added by the adder/subtracter 1, and then returned to the result of the final positive subtraction; the result is stored in register A through the selector 5. Next, the content of this register A is shifted one digit to the left by the shifter 2. That is, it is shifted four bits to the left when a single digit is expressed by four bits. The result 2A is returned to register A through the selector 5.
Next, the content of this register A as a new dividend is reduced by the amount of the divisor in register C, and the result of subtraction is returned to register A through the selector 5. The value of the subtraction count portion 3 is incremented by +1 by the carry detected by the carry detector 4, and the number of the succeeding digits of the quotient is counted.
As described above, the following problems must be solved in order to speed up the operation speed of the decimal division system shown in FIG. 1.
(1) The system consists of a double loop, a subtraction loop and a shift loop for each digit, and these loop processes must be carried out in time sequence.
(2) The process that increments by +1 in the subtraction count portion whenever a carry occurs and which generates the result digit is necessarily separate from the loop process described above.
(3) The process of adding the content of the register C to that of register A is essentially necessary to obtain a partial quotient for a single digit.
To solve only problem (3), a decimal division system has so far been proposed (e.g., Japanese Patent Publication No. 6587/1981).
FIG. 2 is a block diagram of the decimal division system disclosed in the reference described above.
In FIG. 2, a register B has been added so that the results of subtraction by the adder/subtracter 1 are alternately stored in registers A and B, and when a carry no longer occurs, the content of one of the registers which store the positive result is shifted one digit by the shifter 2 and is returned to register A or B, and subtraction is thereafter repeated.
To explain this process more precisely, the problem 1210.div.6=201 with the remainder 4 will be computed.
(a) First of all, "01210000" is stored in register A, and "06000000" is left-packed in register C. PA0 (b) Next, the content of register C is subtracted from the content of register A by the adder/subtracter 1. (Since "06000000" is greater than "01210000", the complement of "06000000", that is, 100000000-06000000=94000000, is added). The result of subtraction, i.e., "95210000", is stored in register B. In this instance, no carry occurs. PA0 (c) The content of register A is shifted one digit (4 bits) to the left, and "12100000" is stored in register A. PA0 (d) The content of register C is subtracted from the content of register A by the adder/subtracter 1, and the result "06100000" is stored in register B. In this case, since a carry occurs, the value of the subtraction count portion 3 becomes "1". PA0 (e) Next, the content of register C is subtracted from the content of register B, and the result "00100000" is stored in register A. Since a carry occurs in this case, the value of the subtraction count portion 3 becomes "2". PA0 (f) The content of register C is subtracted from the content of register A, and the result "94100000" is stored in register B. In this case, the counter is cleared because no carry occurs. PA0 (g) The content of register A is shifted four bits to the left, and "01000000" is stored in the register A. PA0 (h) The content of register C subtracted from the content of register A, and the result is stored in register B. However, since no carry has occurred yet, the content of register A is again shifted four bits to the left, and "10000000" is stored in the register A. PA0 (i) Next, the content of register C is subtracted from the content of register A, and the result "04000000" ia stored in register B. Since a carry occurs in this case, the value of the subtraction count portion 3 becomes "1". PA0 (j) The content of register C is then subtracted from the content of register B, and the result "98000000" is stored in register A. In this case, since no carry occurs, the counter is cleared, and the result is taken as the result digit.
As described above, in FIG. 2, the content of the other register can be used even if either one of the registers, A or B, is negative; hence, the process of adding the divisor to the negative result of subtraction and the computing time can be shortened. Also, since the remainder exists in either of the registers, in the register B in the example described above, it can be simply read out.
To further speed up decimal division instructions, further improvement can no longer be expected because the afore-mentioned problems (1) and (2) have been left yet unsolved.